EVMDM642 APLL Module

The EVMDM642 has an external analog PLL (APLL) which is used to generate input clocks for the external AIC23 codec and internal McASP based S/PDIF controller. It takes an input frequency of 27MHz and generates fixed ratio frequencies in one of two useful frequency groups.

The APLL module defines these two groups as EVMDM642_APLL_FSG0 and EVMDM642_APLL_FSG1 for frequency select group 0 and 1 respectively.

FSG0 generates 18.432 MHz to the AIC23 and 12.288MHz to the McASP AHCLKX0 input. This mode allows the AIC23 to generate sampling rates of 48KHz and its derivatives.

FGS1 generates 16.9344 MHz to the AIC23 and 11.2896 MHz to the McASP AHCLKX0 input. It is used to generate 44.1KHz sampling rates along with its derivatives.

Note: The APLL only sets fixed input clock frequencies to the AIC23 and S/PDIF peripherals. You much still configure each peripheral based on that input clock frequency to obtain a given sample rate. For example, you must set the AIC23’s SAMPLERATE register for 48 KHz operation if that is the frequency you want to use.

Description
Sends a 16-bit mode register value to the APLL.

Required Headers
evmdm642.h
evmdm642_apll.h

Required Libraries
evmdm642bsl.lib

Function Prototype
void EVMDM642_APLL_rset(Uint16 data)

Parameters
data – 16-bit mode value to configure the APLL with.

Return Value
None

Example

    /* Configure the APLL for Freq Select Group 0 (48 KHz) */
    EVMDM642_APLL_rset(EVMDM642_APLL_FSG0);