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EVMDM642 FAQ (720 MHz version) - 10/01/2004

1. Important Notices

2. Video Examples

3. DSP/BIOS Applications

4. DM642 EVM Hardware

5. CCStudio v3.1

1. Important Notices

1.1 Connecting your EVM


When working with the DM642 EVM, be aware that the video inputs, video outputs, JTAG emulator and EVM power supply all have different ground potential levels. You must follow these procedures to prevent damage to your board.

  1. Always attach your JTAG emulator first before any other cables (video inputs/outputs, power) are connected.
  2. When you connect your video input/output cables make sure the video input and video output sources (camera, DVD, etc.) are turned off. After the cables are connected, you should power all inputs and outputs before applying power to the EVM.
  3. Always connect your EVM power supply last after everything else has been connected and powered up.


  1. An XDS560 emulator cannot be manually turned off since it is inside your PC. When you connect the XDS560 to an EVM with nothing else plugged in the EVM's ground will be be brought to the level of your XDS560/PC.

1.2 SDRAM Settings are too fast
The SDRAM settings that originally shipped with the V2 and V3 boards are on the fast side of things. This issue doesn't typically manifest itself in normal EVM operation but it can affect you if you use the EMIF settings as-is on a custom design. You can patch the BSL and GEL file by changing these lines in boards/evmdm642/lib/evmdm642bsl/evmdm642.c from:

    EMIFA_FMKS(SDCTL, TRCD, OF(1))         |
    EMIFA_FMKS(SDCTL, TRP, OF(1))          |
    EMIFA_FMKS(SDCTL, TRC, OF(5))          |
    EMIFA_FMKS(SDCTL, TRCD, OF(2))         |
    EMIFA_FMKS(SDCTL, TRP, OF(2))          |
and these lines in boards/evmdm642/gel/EVMDM642.gel from:
    *(int*)EMIFA_SDRAMCTL   = 0x57115000;   // SDRAM control
    *(int*)EMIFA_SDRAMCTL   = 0x57229000;   // SDRAM control

2. Video Examples

2.1 How to switch the video input from composite to S-Video?
When working with the video examples involving video input signals, the examples are by default set to use the composite RCA input. Each example uses the DDK to communicate with the video decoders, and has a variable of type SAA7115_ConfParams for that purpose.

    SAA7115_ConfParams EVMDM642_vCapParamsSAA7115 = {

To reconfigure the example to run S-Video you have to change the analog input format ( aFmt ) in SAA7115_ConfParams from:
Recompile the code and run.

2.2 Video examples do not run properly when rebuilt under CCStudion v3.1
Check below for information on how to update the TI CSL for CCStudio v3.1

3. DSP/BIOS Applications

3.1 RTDX bug when establishing an emulation connection
There is an RTDX bug that blocks an emulation connection when a DSP/BIOS appilcation with RTDX enabled is running from Flash memory. In order to establish an emulation connection, disable RTDX before writing the program to Flash memory

Follow these steps to disable RTDX:

  1. Go to the Projects Pane -> Projects -> DSP/BIOS Config and open the .cdb file
  2. In the CDB window go to Input/Output -> right click HST-Host Channel Manager and select Properties
    Select NONE for Host Link Type
  3. In the CDB window go to Input/Output -> right click RTDX- Real-Time Data Exchange Settings and select Properties
    Un-check the Enable Real-Time Data Exchange (RTDX)
  4. In the CDB window go to System -> right click Global Settings and select Properties
    Un-check the Enable Real Time Analysis
    Un-check the Enable All TRC Trace Event Classes

With RTDX disabled, the program can run without blocking emulation connections.

4. DM642 EVM Hardware

4.1 Extra circuitry around the FPGA_PROG signal
A logical zero on the FPGA_PROG signal initiates the FPGA programming sequence. This signal is connected to GPIO0 on the DM642 with the intent that whenever you want to reprogram the FPGA you just drop GPIO0 low.

Some extra circuitry (this applies to all publicly available DM642 EVM versions) was added to handle two specific situations.

First, the initial FPGA programming cycle after power up is different from subsequent cycles. The FPGA_PROG signal must be held low after reset for the initial programming operation to work. Typically, this operation is done in the POST running from Flash so that the FPGA is already programmed by the time a normal user tries to run code. In effect, the FPGA_PROG signal should be pulled down until the initial programming sequence has been initiated then driven high by GPIO0.

The second situation is when Code Composer starts up. It issues a soft reset of the processor which pus all GPIOs in their default state (high impedence input). If the FPGA_PROG signal is simply pulled low, FPGA_PROG will drop with every Code Composer start, clearing the FPGA state unexpectedly. The gate attached to FPGA_LOCK uses the DONE signal from the FPGA to handle both of these situations gracefully. Before the initial programming operation, DONE is LOW and FPGA_LOCK will pull FPGA_PROG low to handle the first situation. After the initial programming is complete, DONE will be high and FPGA_LOCK will pull FPGA_PROG high to insure that Code Composer starts will not clear the FPGA.

Note that this circuit may or may not be necessary in your own hardware design. The two situations listed above are specific to the FPGA being used and the way the FPGA is connected to the DSP on the DM642 EVM.

5. CCStudio v3.1

5.1 Examples do not run properly when built under CCStudio v3.1
When DM642 examples are built under CCStudio v3.1, the examples may produce unexpected results. To correct these problems download the latest CSL from the TI website here:

Then proceed to update the project files with the new CSL for CCStudio v3.1. Follow these steps for the CSL update:

  1. Install onto your PC with CCStudio v3.1. (Take note of where you installed the CSL)
  2. Assuming you installed the CSL in directory [User_Install_Dir], all the exisitng CCS project will require that you:
  3. add in compiler options:  -i"[User_Install_Dir]\include"
    add in linker options  :  -l"[User_Install_Dir]\lib"

Begin by updating the library project files( evmdm642bsl.lib, osd.lib, video.lib, and audio.lib ), then each individual example you are having problems with.

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